Lead RTL Design & Validation E · Hyderabad

AMD is seeking a seasoned Lead RTL Design & Validation Engineer to drive DDR memory controller and interface development within the engineering team in Hyderabad.

Key Responsibilities

• Architect and implement micro-architecture specifications for DDR/LPDDR memory controller subsystems.
• Develop clean, synthesis-ready RTL using SystemVerilog and Verilog following strict design guidelines.
• Define test plans, verification architectures, and coverage metrics for complex memory subsystems.
• Implement comprehensive UVM-based validation environments and write complex functional tests.
• Execute RTL simulation, regression testing, and debug failure scenarios down to signal level.
• Perform linting, CDC (Clock Domain Crossing), and formal verification checks across design modules.
• Collaborate closely with physical design teams to resolve timing closure, power, and area constraints.
• Support post-silicon bring-up, silicon validation, and hardware-software integration activities.
• Mentor junior and mid-level RTL engineers in design quality and protocol compliance standards.
• Interface with cross-functional teams to integrate DDR IP into multi-core SoC platforms.
• Drive continuous improvement in RTL design methodologies and front-end verification efficiency.