Staff Engineer, Design Verific · Noida

Synopsys is a global leader in electronic design automation (EDA) and semiconductor IP, driving silicon to software innovations across smart technologies.

Key Responsibilities

• Architect and implement UVM-based testbenches for complex high-speed interface IP protocols.
• Develop detailed verification plans mapping functional requirements to coverage metrics.
• Create constrained-random test sequences and scenarios to thoroughly exercise IP edge cases.
• Implement functional coverage models, covergroups, and assertion-based verification checks (SVA).
• Execute regressions, triage failures, and collaborate with design teams to root-cause RTL bugs.
• Verify high-speed protocol features such as PCIe, USB, Ethernet, or memory interfaces.
• Develop verification automation scripts using Python, Perl, or Shell to optimize regression turnarounds.
• Analyze code coverage and functional coverage metrics to close verification holes systematically.
• Support post-silicon validation and silicon bring-up teams to reproduce and resolve customer-reported issues.
• Review architectural and microarchitectural specifications to define verification boundaries and test strategies.
• Mentor junior verification engineers and enforce verification best practices and coding standards.