Senior Staff Interface IP Veri · Bengaluru

Synopsys is a global leader in electronic design automation (EDA) and semiconductor IP, powering innovations across computing, AI, and automotive systems.

Responsibilities

• Lead pre-silicon verification architecture and strategy for high-speed interface IPs including PCIe, CXL, DDR, and Ethernet.
• Develop scalable, modular, and reusable UVM-based testbenches and verification environments from scratch.
• Author comprehensive verification plans based on architecture and protocol specifications.
• Design and execute directed, random, and constrained-random test sequences for IP validation.
• Define functional coverage models, code coverage metrics, and drive closure to achieve zero-bug silicon delivery.
• Create assertions and checkers to validate interface protocol compliance and timing behaviors.
• Collaborate with digital design teams to debug complex RTL and testbench failures at block and subsystem levels.
• Perform gate-level simulations and debug timing violations alongside physical design engineers.
• Integrate third-party and internal VIPs (Verification IP) into the interface verification platform.
• Drive continuous improvements in testbench automation, regression efficiency, and verification methodology.
• Mentor and guide junior verification engineers across protocol-specific verification activities.