ASIC Digital Design, Sr Engine · Bengaluru

Synopsys is a global leader in electronic design automation (EDA) and semiconductor IP, empowering innovation from silicon to software.

Key Responsibilities

• Drive digital design micro-architecture definitions and specifications for complex ASIC components.
• Develop clean, synthesizable, high-performance RTL coding using Verilog and SystemVerilog.
• Perform linting, CDC (Clock Domain Crossing), and formal verification checks on RTL modules.
• Collaborate closely with verification teams to define comprehensive test plans and debug failures.
• Run synthesis and analyze gate-level designs for area, timing, and power optimization.
• Support Static Timing Analysis (STA) and timing closure across varied operational corners.
• Participate in low-power design methodologies using UPF and power optimization techniques.
• Interface with physical design teams to ensure floorplan feasibility and routability.
• Validate silicon post-silicon bring-up and debug functional issues in the lab environment.
• Mentor junior engineers and adhere to strict ASIC design quality standards.