Senior ASIC Digital Design Eng · Bengaluru

Synopsys is seeking an experienced Senior ASIC Digital Design Engineer in Bengaluru to drive the architecture, RTL design, and verification of high-performance semiconductor solutions.

Key Responsibilities

• Architect and implement complex digital logic using Verilog and SystemVerilog.
• Perform micro-architecture specification development based on system-level requirements.
• Execute RTL synthesis, lint checks, clock domain crossing (CDC), and reset domain analysis.
• Collaborate with verification teams to define test plans and assist in functional debug.
• Conduct static timing analysis (STA) and guide timing closure across operating corners.
• Optimize designs for low power consumption, performance, and silicon area (PPA).
• Work closely with physical design teams to resolve layout, DRC, and timing issues.
• Participate in design reviews and adhere to standard ASIC design methodologies.
• Create behavioral models and simulation testbenches for sub-module verification.
• Debug silicon issues and support post-silicon validation activities in the lab.