Formal Verification Intern · Bengaluru

Synopsys offers an engineering internship in Bengaluru focusing on formal verification methodologies and electronic design automation tools.

Responsibilities

• Learn and apply formal verification processes and methodologies on hardware designs.
• Assist in developing assertions and formal test properties using SystemVerilog Assertions (SVA).
• Support electronic design automation (EDA) workflows and tool verification.
• Run formal verification checks to detect corner-case logic errors and protocol violations.
• Analyze formal verification coverage results and identify unreachable states.
• Collaborate with senior verification engineers to debug proof failures and design issues.
• Write scripts using Python or Perl to automate simulation and formal regression runs.
• Document test results, bug reports, and formal verification findings.
• Contribute to improving internal verification collateral and benchmark designs.
• Participate in design reviews and technical discussions within the engineering team.